Sense amplifier for semiconductor memory device

ABSTRACT

A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

TECHNICAL FILED OF THE INVENTION

The present invention relates to a random access memory and,particularly, to a memory in which a signal read from a memory cell to abit line is transmitted to a peripheral circuit at a high speed by agate-input amplifier.

BACKGROUND OF THE INVENTION

Japanese Patent Laid-Open No. 11-306762 (hereinafter referred to as“Document”) discloses, as shown in FIG. 23, an SRAM memory array inwhich each bit line BL/BLB is provided with a column sense amplifier CSAto be connected to a global bit line GBL/GBLB. In this structure, thecolumn sense amplifier can be selectively activated by a sense amplifieractivating signal S for each block and a Y address signal YB, so thatpower consumption can be reduced.

Prior to the present invention, the inventors of the present inventionhave studied a control method used in the case where a potential of abit line of DRAM is detected by a differential, gate-receivingamplifier, i.e., by a so-called direct sense amplifier. They havenoticed the following points to be considered when the amplifier controlmethod in the above-mentioned Document is used for the direct senseamplifier of DRAM. Firstly, since large-sized MOS transistors MN 20 andMN 21 are directly connected to a global bit line (corresponding to alocal IO line to be connected to an output of the direct sense amplifierin DRAM), a load capacity of the global bit line (local IO line) isincreased. In the DRAM, a number of direct sense amplifiers, e.g.,approximately 32 to 128 direct sense amplifiers are normally connectedto the local IO line. Also, since the local IO line and a main IO linelying ahead have long distances and large loads and the gates of the MOStransistors serving as a differential pair are long in order to reduce athreshold voltage offset, the gate width of the MN 20 and MN 21 isrequired to be, for example, 4 μm or longer. Therefore, like the CSA asshown in FIG. 23, in the structure where all differential pairs of anon-selected direct sense amplifier are visible, the load capacity ofthe local IO line is heavy, so that an operation with a high speed isdifficult.

Secondly, the bit-line pre-charge level of DRAM is half of a level VDLof a power-supply voltage or a level VDL obtained by lowering thepower-supply voltage, that is, VDL/2. Therefore, when a negative signaloccurs on the BL and the level of the BL is decreased to a level lowerthan VDL/2, the MN 21 is cut off and the channel capacitance of MN 21 ismade invisible from the local IO line. However when a positive signaloccurs on the BL and the level of the BL is increased to a level higherthan VDL/2, the MN 21 is conducted and the channel capacity is madevisible. Therefore, the capacity of the local IO line is significantlychanged depending on a data pattern on the bit line. That is, aoperational speed is significantly changed depending on a operationcondition, so that there is the problem that a post-manufacturing testis made complicated.

Therefore, a first object to be solved by the present invention is tohave a configuration in which a direct sense amplifier in a randomaccess memory such as DRAM or SRAM can be selectively activated, whereinthe load capacity of a local IO line is reduced and also its datapattern dependency is reduced. Also, a second problem to be solved bythe present invention is to reduce noise in the direct sense amplifierin performing an operation at a high speed and to increase an operationmargin. Furthermore, a third problem in the present invention is todouble the number of bits to be read from a single memory array withoutincreasing chip size.

The above and other objects and effects in the present invention will beapparent from the description of this specification and the accompanyingdrawings.

DISCLOSURE OF THE INVENTION

A representative configuration of the present invention will bedescribed as follows.

That is, a semiconductor memory device comprises: first and secondregions each including a word line extending in a first direction, firstand second bit lines extending in a second direction intersecting withsaid first direction, a memory cell connected to said word line and saidfirst and second bit lines, an amplifier circuit for amplifyinginformation read from said memory cell, first and second IO lines forreceiving the read information from said amplifier circuit, and a sourceline for controlling said amplifier circuit; and a column select lineconnected to said first and second regions in common and extending insaid second direction, wherein said amplifier circuit includes first tofourth MOS transistors, a gate of said first MOS transistor is connectedto said first bit line, a gate of said second MOS transistor isconnected to said second bit line, and sources of said first and secondMOS transistors are connected to said source line; a drain of said thirdMOS transistor is connected to said first IO line and a drain of saidfourth MOS transistor is connected to said second IO line; gates of saidthird and fourth MOS transistors included respectively in the amplifiercircuits are connected to said column select line in common; a drain ofsaid first MOS transistor is connected to a source of said third MOStransistor; a drain of said second MOS transistor is connected to asource of said fourth MOS transistor; and in a first state, potentialsof said first and second IO lines included in said first region arehigher than a potential of the source line included in said firstregion, and the first and second IO lines included in said second regionand the source line are equal in potential.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows memory arrays and sense amplifiers.

FIG. 2 shows a chip structure and a memory block structure of asemiconductor memory device according to the present invention.

FIG. 3 shows a layout and a sectional view of a memory array.

FIG. 4 is circuit diagrams of a sub-word driver and a sub-word driverarray.

FIG. 5 is a circuit diagram of a cross area.

FIG. 6 is a circuit diagram of a main amplifier.

FIG. 7 is a block diagram of a data path during reading.

FIG. 8 shows operation waveforms during the reading.

FIG. 9 shows the operation waveforms to be continued during the reading.

FIG. 10 is a block diagram of a data path during writing.

FIG. 11 shows operation waveforms during the writing.

FIG. 12 shows the operation waveforms to be continued during thewriting.

FIG. 13 is a circuit diagram of a second sense amplifier.

FIG. 14 is a circuit diagram of a third sense amplifier.

FIG. 15 is a circuit diagram of a fourth sense amplifier.

FIG. 16 shows operation waveforms of the third sense amplifier.

FIG. 17 is a circuit diagram of a second main amplifier.

FIG. 18 is a circuit diagram of a third main amplifier.

FIG. 19 is a circuit diagram of a fourth main amplifier.

FIG. 20 shows a connection method of a second local IO according to thepresent invention.

FIG. 21 shows a second data path structure according to the presentinvention.

FIG. 22 shows operation waveforms on the second data path during thereading.

FIG. 23 is a block diagram of a column sense amplifier scheme of aconventional SRAM.

BEST MODE FOR CARRYING OUT THE INVENTION

For describing the present invention at detail, it will be describedbased on the accompanying drawings. Note that, throughout all of thedrawings for explaining embodiments, components having the same functionare denoted by the same reference numeral and the repetition thereofwill be omitted.

First Embodiment

FIG. 1 shows memory arrays ARY and sense amplifiers SA according to thepresent invention. To describe a function of the sense amplifier, a chipstructure of a semiconductor memory device according to the presentinvention is shown in FIG. 2A. The entire chip CHIP is broadly dividedinto a control circuit CNTL, input/output circuits DQC, and memoryblocks BLK. A clock, an address, and a control signal are supplied tothe control circuit from the outside of the chip to determine anoperation mode of the chip and pre-decode the address. The input/outputcircuit includes an input/output buffer, so that write date is inputtedfrom the outside of the chip and read data is outputted to the outsideof the chip.

A structure of the memory block BLK is shown in FIG. 2B. On the memoryblock, memory arrays ARY are disposed on a plurality of arrays, and areeach surrounded by sense amplifier columns SAA, sub-word driver columnsSWDA, and cross areas XP. Also, column decoders YDEC and main amplifiercolumns MAA are disposed in an outer circumference so as to be parallelto the sense amplifier columns, and row decoders XDEC and array controlcircuits ACC are disposed so as to be parallel to the sub-word drivercolumns.

FIG. 1 shows two memory arrays and the sense amplifier columns disposedtherebetween. The sense amplifier according to the present inventionincludes transfer gates TGC, a pre-charge circuit PCC, a restoreamplifier CC, a write circuit WP, and an amplifier circuit, i.e., adirect sense amplifier DSA. The transfer gate is a circuit forconnecting the sense amplifier and the memory arrays when asense-amplifier separation signal SHR is activated. The pre-chargecircuit equalizes a line between bit lines to be a pair when apre-charge signal PC is activated and pre-charges it to a bit-linepre-charge level. The bit-line pre-charge level is normally set to amidpoint of a bit-line amplitude VDL (a level equal to a power supplyvoltage from the outside of the chip or a level obtained by lowering thepower supply voltage), i.e., VDL/2. When the above-described twin-cellarchitecture is used, the pre-charge level can be set to a high levelVDL or a low level VSS of the bit line even without using a dummy cellfor generating a reference voltage. However, the direct sense amplifier,which will be described further below, has a high trans-conductance whenthe level of the bit line is approximately VDL/2, so that it isdesirable that the bit-line pre-charge level is set to VDL/2 for ahigh-speed operation. The restore amplifier is a circuit which, afteroccurrence of a subtle read signal from the memory cell on the bit line,drives a P-side common source line CSP at the VDL and an N-side commonsource line CSN at the VSS and amplifies the high-voltage one of the bitlines BL and BLB to the VDL and the low-voltage one to the VSS.

The write circuit WP is a circuit for connecting write local IO linesWLIO/WLIOB and a bit-line pair when a write column select line WYS isactivated. In order to prevent current consumption at the unselectedsense amplifier column, the WLIO is pre-charged to the VBLR at a time ofpre-charged period. The direct sense amplifier DSA is a circuit fordriving read local IO lines RLIO/RLIOB by a subtle signal occurring onthe bit line and for transmitting a signal. During the pre-chargedperiod, the RLIO is pre-charged to an IO-line pre-charge level VPC. Adirect-sense-amplifier common source line DSAS is pre-charged to anIO-line pre-charge level VPC during the pre-charged period and is drivenat the VSS at a time of a read operation.

In the sense amplifier, when a read-column select line RYS is activated,the DSAS is driven at the VSS on the selected sense amplifier column andthe DSAS is kept at the VPC on the non-selected sense amplifier column.Therefore, there is an advantage of being capable of activating only theselected sense amplifier and preventing the current consumption on theunselected sense amplifier. Also, in this amplifier, small-sized MOStransistors MN2 and MN3 (for example, each having a gate width of 1 μm)controlled by the RYS are disposed between each of large-sized MOStransistors MN0 and MN1 (for example, each having a gate width of 4 μm)serving as a differential pair having a bit separated from each other.Therefore, in the unselected direct sense amplifier in which the RYS isset at the YSS, since the channel capacitance of the differential pairis not viewable from the RLIO line, it is possible to reduce a parasiticcapacitance of the RLIO line and also prevent the parasitic capacitancefrom being changed depending on the data pattern on the bit line.

The memory array includes a plurality of memory cells MC. In thisembodiment, the memory cell has a twin-cell architecture including twoDRAM cells. The DRAM cell includes one MOS transistor and one capacitor,wherein one of a source and drain of the MOS transistor is connected tothe bit line and the other of the source and drain is connected to astorage node SN and a gate thereof is connected to the word line. Oneterminal of the capacitor is connected to the storage node SN and theother terminal of the capacitor is connected to a plate electrode PLcommon to the other cells. In the twin cell, two DRAM cells areconnected to the common word line and the bit lines to be a pair, andinformation is stored by writing complementary data in the storage nodeof each cell. In the following, the twin cell is used for describing thepresent invention. However, the sense amplifier according to the presentinvention can be applied to the case where one DRAM cell is used as amemory cell. When such a twin cell is used, a signal amount of bit lineis approximately doubled in comparison with the case where only a singleDRAM cell is used. When the direct sense amplifier as shown in FIG. 1 isused, the signal generated from the memory cell can be converted to acurrent difference by the direct sense amplifier without being amplifiedby the restore amplifier and then read to the local IO line. Therefore,as the signal amount on the bit line is larger, the signal amount to beread to the local IO line is larger. Thus, in a combination of thedirect sense amplifier and the twin-cell architecture, the furtherenhanced speed can be achieved.

FIG. 3A shows a layout of the memory array and FIG. 3B shows a sectionalview taken along the A–A′ thereof. The DRAM cell includes an N-channelMOS transistor formed in a substrate PW, and a stack capacitor providedat an upper portion of the bit line BL. An active region of the MOStransistor is denoted by “ACT”, a word line is denoted by “WL”, andN-type diffusion layer region is denoted by “N”. The active region isseparated by an insulator of SiO2. Contacts CB are disposed at an upperportion of a diffusion layer, and a bit-line contact BC or astorage-node contact SC is disposed on the upper portion thereof. At anupper portion of the bit-line contact, the bit line BL is disposed in adirection orthogonal to the word lines. On the storage-node contact, theconcave storage node SN is disposed. The plate electrode PL is embeddedinside the storage node, and these form a capacitor in a state ofsandwiching a capacitance insulating film CI therebetween. The presentmemory array is an open-bit-line type memory array in which the DRAMcells are connected to all intersection points of the bit line and theword line, so that the word line can be reduced to 2F (F: minimumprocessing size) and the bit line pitch can be reduced to 3F. In thisembodiment, the two DRAM cells are used as a single memory cell toachieve a memory cell having a twin-cell architecture. However, thereare the cases where two adjacent DRAM cells become a pair similarly toMCa and two separated DRAM cells become a pair similarly to MCb. Thus,when two cells each having one intersection point are used to form thetwin cell, their cell size becomes the square of 12F, so that an areathereof can be reduced in comparison with the case of using two cellseach having two intersection points. Also, unlike the normal cells eachhaving one intersection point, since the bit line to be a pair can bedisposed on the same array, there is an advantage such that noiseoccurring during sensing, which becomes a problem in the cells eachhaving one intersection point, can be prevented.

FIG. 4 is a circuit diagram of a sub-word driver SWD and a sub-worddriver array SWDA configured by disposing a plurality of sub-worddrivers. The sub-word driver includes two N-channel MOS transistors andone P-channel MOS transistor. One of the N-channel MOS transistors has agate connected to a main word line MWLB, a drain connected to the wordline WL, and a source connected to a ground VSS. The other of theN-channel MOS transistors has a gate connected to a complementaryword-driver select line FXB, a drain connected to the word line WL, anda source connected to the ground potential VSS. The P-channel MOStransistor has a gate connected to the main word line MWLB, a drainconnected to the word line WL, and a source connected to a word-driverselect line FX. As shown in Figure, four lines FX are wired on one SWDA,and any one of four drivers SWD that is selected on one MWLB is selectedto activate one WL. Also, in an upper portion of or a region adjacent tothe sub-word driver column, main IO line pairs MIO/MIOB are wired.

FIG. 5 is a circuit diagram of the cross area XP. The cross areaincludes an SHR-signal driver SHD, an RLIO-line pre-charge circuit RPC,a read gate RGC, a DSAS-line driver DSAD, a WLIO-line pre-charge circuitWPC, a write gate WGC, a CS-line driver CSD, a CS-line pre-chargecircuit SPC, a PC-signal driver PCD, and an FX-line driver FXD. TheSHR-signal driver, in which a complimentary signal SHRB of the senseamplifier separation signal SHRB is inputted, outputs the SHR. TheRLIO-line pre-charge circuit pre-charges the RLIO line to the VPC when aread enable signal RE is inactive at a VSS level. The read gate is acircuit for connecting the RLIO line and the main 10 lines MIO/MIOB whenRE is at an activated VCL (used as a peripheral-circuit power-supplyvoltage at a level equal to the external VCC level or a level obtainedby lowering it). At this time, in the case of setting the VPC to theVCL/2, a large on-state current of NMOS can be obtained even when onlythe NMOS is used to form the read gate. Therefore, a load of MIO can bemade smaller than the case of the CMOS structure, and the signal on theMIO line can be increased. Also, even when the VPC is set to the VCL/2,there is no harm in reducing a threshold voltage of the NMOS used forthe direct sense amplifier. The DSAS-line driver is a circuit forpre-charging the DSAS to the VPC when the RE is inactive and for drivingthe DSAS at the VSS when the RE is activated. As such, by disposing theDSAS-line driver on the cross area, the DSAS line can be activated inunits of mats. Therefore, the direct sense amplifier can be activatedonly at the selected mat, whereby power consumption can be reduced.Also, in FIG. 2, in comparison to the case where the DSAS line driversare disposed so as to be concentrated in a portion of the array controlcircuit ACC, a potential difference between far and near ends on theDSAS line becomes small due to an effect of dispersion and dispositionof the drivers, so that there is an advantage such that variations insense speeds depending on the location of the direct sense amplifier canbe reduced.

The WLIO-line pre-charge circuit pre-charges the WLIO line to the VDL/2when a write-enable signal WE is set at the inactive VSS level. Thewrite gate is a circuit for connecting the WLIO line and the main IOlines MIO/MIOB when the WE is set at the active VCL level. In the casewhere the present circuit has a CMOS configuration, when write isperformed from the MIO line to the WLIO line, the VCL level and the VSSlevel can be outputted without reduction in amplitude. The CS-linedriver is a circuit for driving a P-side common source line CSP at theVDL (H level of the bit line) and an N-side common source line CSN atthe VSS when a sense-amplifier enable signal SE is active. The CS-linepre-charge circuit SPC is a circuit for pre-charging the CSP and CSN atthe VDL/2 when a pre-charge signal PC is activated. The PC-signaldriver, into which a complementary signal PCB of the pre-charge signalPC is inputted, outputs the PC. The FX-line driver, into which acomplementary signal FXB of the FX line is inputted, outputs the FX.

FIG. 6 shows a main amplifier circuit MA. The main amplifier circuitincludes a MIO pre-charge circuit IPC, a load circuit LD, a transfergate TGC, an MA pre-charge circuit APC, a latch circuit LTC, a GIObuffer GB, and a write buffer WB. The MIO pre-charge circuit pre-chargesan MIO line at the VPC when an MIO pre-charge signal IP is activated.The load circuit functions as a load on the MIO line when a transfergate control signal TG is activated and its complementary signal TGB isset at the VSS. The transfer gate is conducted when the TG is activated,thereby connecting the MIO and the latch circuit. The main amplifierpre-charge circuit APC pre-charges the inside of the main amplifier tothe VPC when the main amplifier pre-charge signal AP is activated. Thelatch circuit is a circuit for amplifying, to a full amplitude (VCL,i.e., the power-supply potential or VSS), a signal having a smallamplitude inputted from the MIO and for retaining the full amplitude.The GIO buffer is a circuit for outputs data retained in the latchcircuit to a read global IO line GIOR when a GIO buffer enable signalGBE is activated. The write buffer WB is a circuit for outputting dataon a write global IO line GIOW to the MIO/MIOB when a write bufferenable signal WBE is activated.

To illustrate a read operation, FIG. 7 shows a block diagram of twomemory arrays ARY0, ARY1 and three sense amplifier columns SAA0 to SAA2,which are part of FIG. 1. In this drawing, the read column select linesRYS in every sense amplifier column are connected to one direct senseamplifier DSA, but may be connected to a plurality of direct senseamplifiers. In this case, it is accordingly required to increase thenumber of read LIO pairs. Also, two pairs of MIO0/MIOB0 and MIO1/MIOB1are alternately connected to the read gate circuit in the cross area.Therefore, when the word line WL0 and the RYS0 are activated, pieces ofdata are read to the sense amplifier columns SAA0 and SAA1 and thesepieces of data are read via the RLIO0/RLIOB0 and RLIO1/RLIOB1 to theMIO0/MIOB0 and MIO1/MIOB1, respectively.

A read operation will be described by using operation waveforms in FIG.8. When a read command RD is inputted from the outside of the chip, thesense amplifier separation signal SHR and the pre-charge signal PC aredeactivated in the sense amplifier columns SAA0 and SAA1 specified byaddresses. Furthermore, the read enable signal RE is activated, and thedirect-sense-amplifier common source lines DSAS0 and DSAS1 are driven atthe VSS. Here, when the RYS0 is activated by the column decoder, thedirect sense amplifiers start operating in the sense amplifier columnsSAA0 and SAA1. At this time, in the unselected sense amplifier columnSAA2, since the RLIO2/RLIOB2 have the same potentials as that of theDSAS2, a penetrating current does not flow therebetween. Similarly, alsoin the other unselected sense amplifiers, since a penetrating currentdoes not flow therebetween, current consumption can be reduced. Notethat the same potential in this case is that a potential differencebetween the RLIO2/RLIOB2 and the DSAS2 is at a level at which the directsense amplifier connected to their lines does not start operating. Thecurrent consumption can also be reduced, by setting both of theRI02/RIO2B and the DSAS to have a voltage equal to or more than a valueobtained by subtracting a threshold voltage of the NMOS used for theDSAS from the bit line potential VDL/2. As evident from the blockdiagram of FIG. 1, since the RYS is connected to a number of senseamplifier columns, this circuit scheme is effective in reducing anoperation current. Also, it is possible to prevent a penetratingcurrent, by setting an absolute value of a potential difference betweenthe RLIO/RIOB and the common source line DSAS connected to the selectedsense amplifier column to be larger than an absolute value of apotential difference between the RLIO/RIOB and the common source lineDSAS connected to the unselected sense amplifier column. In this way, asimilar effect can be obtained, by setting a current flowing between thesource and drain of the transistor connecting the unselected senseamplifier and the bit line to be less than a current flowing between thesource and drain of the transistor connecting the selected senseamplifier and the bit line.

When the main word line MWLB is decreased to the VSS in the row decoderand the FX is activated in the array control circuit ACC, the selectedword line WL0 is activated to the VPP. In the memory cell selected bythe word line WL, a cell transistor is conducted and a signal is read tothe bit line BL. Here, since the memory cell has a twin-cellarchitecture, one of the BL/BLB is higher than a pre-charge level of thebit line and the other is lower than that. Upon reception of the signalon the bit line, the direct sense amplifier drives the RLIO/RLIOB,whereby a voltage difference occurs on the RLIO/RLIOB. Since the readgate becomes conducted in the cross area by the RE, this signal istransmitted to the MIO/MIOB. Also, in the present embodiment, after theRYS0 is activated and the DSAS0 and DSAS1 are driven at the VSS, theword line WL is activated the RYS0. However, the WL can be startedbefore the RYS0 and DSAS0 and DSAS1 are driven. By doing so, operationmargin can be reduced more than that of the normal sense amplifier.

The operation following thereafter will be described with reference toFIG. 9. Almost at the same time when the RE is activated, the transfergate control signal TG is activated. Therefore, a signal on the MIO isinputted to the latch in the main amplifier. At timing when the signalbecomes sufficiently large at an input end of the latch, the TG isdeactivated and the latch signal is activated and then the data is fixedand retained. Thereafter, the GIO buffer enable signal GBE is activated,data is forwarded to the output circuit DQC via the read global IO lineGIOR, and the data is outputted to a DQ. When a fix of the data by thelatch is completed, the pre-charging is started at the RLIO line pairs,the MIO line pairs, and the DSAS line used for reading.

At the same time of reading the data subsequently to the direct senseamplifier, a re-write operation is performed in the memory array. Asshown in FIG. 8, when the P-side common source line CSP is driven at theVDL and the N-side common source line CSN is driven at the VSS, therestore amplifier CC in the sense amplifier amplifies the bit line tothe VDL or VSS. The word line is deactivated to the VSS at the timingwhen the data is sufficiently written in the memory cell. In the senseamplifier column, the PC and SHR are activated and the bit line and thecommon source line are pre-charged, whereby a read cycle ends.Therefore, by using the direct sense amplifier, the data reading and are-write operation of the memory array can be performed in parallel.Therefore, while the direct sense amplifier is stared earlier than thecase where the word line is activated and thereby the reading of thedata is speeded up, the restore amplifier is started after the word lineis activated and the signal from the memory cell sufficiently occurs onthe bit line, so that a highly reliable re-write operation can beperformed.

To illustrate a write operation, FIG. 10 shows a block diagram of twomemory arrays ARY0 and ARY1 and three sense amplifier columns SAA0 toSAA2, which are part of FIG. 1. In this Figure, the write column selectlines WYS in every sense amplifier column are connected to one writecircuit WP, but may be connected to a plurality of write circuits. Inthis case, it is accordingly required to increase the number of writeLIO pairs. Also, two pairs of MIO0/MIOB0 and MIO1/MIOB1 are alternatelyconnected to the write gate circuit in a cross area. Therefore, when theword line WL0 and the WYS0 are activated, pieces of data on theMIO0/MIOB0 and MIO1/MIOB1 are written from the write circuits in thesense amplifier columns SAA0 and SAA1 via the WLIO0/WLIOB0 andWLIO1/WLIOB1 to the data line and the memory cell of the memory array,respectively.

A write operation will be described by using operation waveforms in FIG.11. When a write command WT is inputted from the outside of the chip,write data is captured from the DQ and is then outputted to the writeglobal IO line GIOW. When the MIO pre-charge signal IP is deactivatedand the write buffer enable WBE is activated, write data is outputted tothe MIO line.

An array operation following thereafter will be described with referenceto FIG. 12. When the write command WT is inputted from the outside ofthe chip, the sense-amplifier separation signal SHR and the pre-chargesignal PC are deactivated in the sense amplifier columns SAA0 and SAA1specified by addresses. Furthermore, the write enable signal WE isactivated and the write gate is conducted in the cross area, whereby thewrite data is written from the MIO/MIOB to the WLIO/WLIOB. When the WYS0is activated by the column decoder, writing to the bit line of thememory array is started. At this time, in the unselected sense amplifiercolumn SAA2, the WLIO2/WLIOB2 remain at the VDL/2. Therefore, even ifthese are connected to the bit line, they have the same potential asthat of the bit line and thus no current flows. The same occurs even inthe other unselected sense amplifier columns. As evident from the blockdiagram of FIG. 1, since the WYS is connected to a number of senseamplifier columns, this circuit scheme is effective in reducing anoperation current.

When the main word line MWLB is decreased to the VSS in the row decoderand the FX is activated in the array control circuit ACC, the selectedword line WL0 is activated to the VPP. In the memory cell selected bythe word line WL, a cell transistor is conducted, and data is writtenfrom the bit line to the memory cell. Furthermore, when the P-sidecommon source line CSP is driven at the VDL and the N-side common sourceline CSN is driven at the VSS, the restore amplifier CC in the senseamplifier amplifies the bit line to the VDL or VSS. Upon completion ofthe data writing to the memory array, the WE is deactivated, the WLIOand MIO are cut off, and the WLIO and MIO are pre-charged. The word lineis deactivated to the VSS at the timing when data is sufficientlywritten in the memory cell. In the sense amplifier column, the PC andSHR are activated, and the bit line and the common source line arepre-charged, whereby a write cycle ends.

FIG. 13 shows a circuit of a second sense amplifier SA. In this senseamplifier, two SAs share a set of the direct sense amplifier DSA and thewrite circuit WP. For this reason, by adding selecting means such as amultiplexer MUX and selecting either one of the S0 and S1, t is selectedwhich of the two SAs is connected to the RLIO/RLIOB or WLIO/WLIOB.Respective circuits and operations of the transfer gate TGC, thepre-charge circuit PCC, the restore amplifier CC, the write circuit WP,and the direct sense amplifier DSA are the same as those shown inFIG. 1. In this sense amplifier, in addition to having the same effectsas those of the sense amplifier of FIG. 1, since the direct senseamplifier DSA can be disposed in a region for the two sense amplifiers,it is possible to increase the size of the MOS transistor in the directsense amplifier DSA and increase the signal amounts read in theRLIO/RLIOB and the MIO/MIOB. Thus, since the load capacitance of the bitline is increased by adding the multiplexer into the sense amplifier,the signal amount of bit line is reduced. However, as shown in theFigure, since the twin cell is used in the present invention, the signalamount of bit line is approximately twice as much as the case where onenormal DRAM cell is used. Therefore, there is an advantage in which aninfluence of reduction in the signal amount of bit line becomes smalldue to the addition of the multiplexer.

FIG. 14 shows a circuit of a third sense amplifier SA. In this senseamplifier, the select line YS is common to reading and writing. For thisreason, in the write circuit WP, the MOS transistor controlled by thewrite enable signal WE is connected in series to the MOS transistorcontrolled by the column select line. Since the WE is deactivated duringthe reading, the sense amplifier and the WLIO/WLIOB are not connectedeven if the column select line YS is activated. The circuits andoperations of the transfer gate TGC, the pre-charge circuit PCC, therestore amplifier CC, and the direct sense amplifier DSA are the same asthose shown in FIG. 1. In this sense amplifier, in addition to havingthe same effects as those of the sense amplifier of FIG. 1, the numberof column select lines is reduced by half in comparison with the senseamplifier of FIG. 1. Therefore, a process can be facilitated byexpanding the wiring pitch, and the operation of the sense amplifier canbe speeded up by increasing the number of power-supply wirings.

FIG. 15 shows a circuit of a fourth sense amplifier SA. In this senseamplifier, an equalizing MOS transistor MN4 is connected betweenconnection points N0 and N1, which connects the MOS transistors MN2 andMN3 controlled by the column select line YS in the direct senseamplifier DSA and the MOS transistors MN0 and MN1 each having a gateconnected to the bit line, respectively, in the sense amplifier of FIG.14. When the pre-charge signal PC is activated, this MOS transistor isconducted, thereby short-circuiting them between the points N0 and N1.Operation waveforms of the sense amplifier of FIG. 14, which has no MN4,are shown in FIG. 16. As for the sense amplifier in which the YS isunselected during a read operation, when the DSAS is driven at the VSS,the points N0 and N1 each have a potential of VSS. If the DSAS isrecovered to the VPC with the bit lines BL and BLB being amplified tothe VDL and VSS, respectively, the point N0 becomes at the VPC and thepoint N1 remains at the VSS since the MN0 is in an ON state and the MN1is an OFF state. If the bit line is pre-charged, the point N0 remains atthe VPC. However, since the gate of the MN0 is at the VDL/2, the pointN1 is increased only up to “VDL/2−VT”. In this case, “VT” is a thresholdvoltage of the MN1. Therefore, with the bit line being pre-charged, apotential difference occurs between the points N0 and N1. When the DSASis driven at the VSS in the next read cycle, the potentials of thepoints N0 and N1 are again decreased to the VSS. At this time, however,since a coupling voltage returned to the bit lines via the MN0 and MN1becomes unbalanced between the BL and BLB, this causes noise to thesense amplifier. In the sense amplifier of FIG. 15, to which theequalizing MOS transistor MN4 is added, since a potential differencebetween the points N0 and N1 during the pre-charging can be eliminated,it is possible to reduce the noise during the operation and achieve thestable circuit operation.

Also, in the write circuit WP of the sense amplifier of FIG. 15, anequalizing MOS transistor MN9 is connected between connection points N2and N3, which connect MOS transistors MN7 and MN8 controlled by thecolumn select line YS and MOS transistors MN5 and MN6 controlled by thewrite enable signal WE, respectively. This MOS transistor is conductedwhen the pre-charge signal PC is activated, thereby short-circuitingthem between the points N2 and N3. In the case of the sense amplifier ofFIG. 14, which has no MN9, if the WE is returned to the VSS with the bitline BL and BLB being amplified to the VDL and VSS during the writeoperation, the points N2 and N3 remain at the VDL and VSS, respectively.The electric charges stored in these nodes are retained during thepre-charging, so that they flow to the BL and BLB when the WE isactivated in the next write cycle. Therefore, by adding the equalizingMOS transistor MN9 thereto, it is possible to reduce the noise duringthe operation and achieve the stable circuit operation. Here, in thecase of the sense amplifier of FIG. 14, if the WE is activated duringthe pre-charging and is deactivated only during the read operation, theMN9 may be not connected thereto. However, in this case, unlessdeactivation of the WE is made earlier than activation of the word line,the read signal from the memory cell on the bit line, in which the YS isselected, flows to the LIO via the MN5 to MN8. Accordingly, in the senseamplifier of FIG. 15, if the WE is deactivated during the pre-chargingand is activated only during the write operation, a timing margin duringthe operation can be alleviated.

Note that FIG. 15 illustrates the case where the column select lineconnected to the direct sense amplifier DSA and the column select lineconnected to the write circuit WP are the same. However, the same effectcan be achieved even if these are separated. Even in such a case, toperform a write mask operation in which write is stopped by any of thesense amplifiers selected by the WYS and DSAS during the writingoperation, the MN5 and MN6 are required and providing the MN9 becomeseffective in order to solve such problems described above.

FIG. 17 shows a second main amplifier circuit MA. This main amplifierincludes an MIO pre-charge circuit IPC, a load circuit LD, an MApre-charge circuit APC, a latch circuit LTC, a GIO buffer GB, and awrite buffer WB. The MIO pre-charge circuit pre-charges the MIO line tothe VPC when the MIO pre-charge signal IP is activated. The load circuitfunctions as a load on the MIO line when the read enable signal RE isactivated and the REB is at the VSS. The main amplifier pre-chargecircuit pre-charges an output node of the latch to a VCL (power-supplypotential) when a complementary main amplifier pre-charge signal APB isat the VSS. The latch circuit is a circuit for amplifying, to a fullamplitude (VCL or VSS), a signal having a small amplitude inputted fromthe MIO at a time of activation of the latch signal LT and for retainingit. The latch circuit of this main amplifier is different from the latchcircuit of the main amplifier of FIG. 6 in that the gate-input amplifierand the cross couple are used. Therefore, since the input capacitanceviewed from the MIO line is reduced, an input signal of the mainamplifier can be increased, so that there is an advantage of having ahigh operation speed. Meanwhile, if the MIO level is too lowered, thereis the problem that a conductance of the MOS transistor whose gate isinputted to the MIO is decreased and the operation speed becomes lateTherefore, in view of the operation margin, the first main amplifier ofFIG. 6 of the operation margin, the first main amplifier of FIG. 6 ismore advantageous. The structures of the GIO buffer and the write bufferWB are the same as those of the main amplifier of FIG. 6.

FIG. 18 shows a third main amplifier circuit MA. In this main amplifier,the load circuit LD and the transfer gate TGC in the first mainamplifier circuit of FIG. 6 are exchanged only in position, and theother circuits are much the same. Thus, since the load circuit isprovided inside of the transfer gate of the N-type MOS transistor withrespect to the main IO, these operate as a common gate amplifier.Therefore, a signal difference between the MIO0/MIOB0 is amplified andtransmitted to inputs LN and LNB of the latch. Accordingly, the inputsignal of the latch circuit is increased, so that there are advantagesof improving the operation speed of the latch and enhancing theoperation margin.

FIG. 19 shows a fourth main amplifier circuit MA. In this mainamplifier, the common gate amplifier GA in the third main amplifier ofFIG. 18 is combined with the latch circuit LTC of FIG. 17. In additionthereto, a source follower circuit SF is provided between the LTC andthe GA for impedance conversion. In this circuit, the input signal canbe pre-amplified by the common gate amplifier, and the input capacitanceof the latch-type amplifier is small. Therefore, there is an advantageof making it possible to increase the signal amount and perform anoperation of a wide margin at a high speed. Furthermore, since thesource-follower circuit is provided, it is possible to reduce couplingnoise added from a differential MOS transistor of the latch amplifier tothe input terminal at the time of starting the latch amplifier. Stillfurther, input and output of the latch amplifier LTC are separated inthis main amplifier, so that the output node of the latch amplifier canbe pre-charged to the VCL. Therefore, the gate of the NMOS in the GIObuffer is in a cut-off state at the VSS, so that before the LT isinputted and the latch fixes data, if the GBE is inputted and the GIObuffer is activated, the GIO buffer can be driven only at the timing ofthe latch. Accordingly, an access can be made at a higher speed.

Second Embodiment

FIG. 20 shows a connection method of a second local IO according to thepresent invention. By using this connection method, when the directsense amplifier DSA and the write circuit WP in one sense amplifier SAare connected to different local IO lines, data of two bits can be readfrom one sense amplifier column during the reading and writing by usingtwo set of LIO line pairs.

For this reason, the sense amplifiers are divided into a group “a” and agroup “b” at a center of one sense amplifier column SAA. In the group“a”, the write circuit WP is connected to one local IO line pairLIO0/LIO0B, and the direct sense amplifier DSA is connected to the otherlocal IO line pair LIO1/LIOB1. Conversely in the group “b”, the writecircuit WP is connected to the local IO line pair LIO1/LIO1B, and thedirect sense amplifier DSA is connected to the other local IO line pairLIO1/LIOB1.

During the reading, when one RYS is activated from each of the groups“a” and “b”, the data from the sense amplifiers in the group “a” is readto the LIO1 and LIOB1, and data from the sense amplifiers in the group“b” is read to the LIO0 and LIOB0. During the writing, when one WYS isactivated from each of the groups “a” and “b”, data can be read to thesense amplifiers in the group “a” by using the LIO0 and LIOB0 and datacan be read to the sense amplifiers in the group “b” by using the LI01and LIOB1. In contrast, when the plurality of RYSs are activated in FIG.7, pieces of data read from the plurality of sense amplifiers collidewith one another on the same LIO. Also, when the plurality of WYSs areactivated in FIG. 10, the same data is written in the plurality of senseamplifiers. Therefore, according to the connection method for the localIO of the present invention as shown in FIG. 20, the number of bitsreadable or writable from one sense amplifier column can be increasedtwice without increasing the number of wirings of the LIO lines.

Third Embodiment

FIG. 21 shows a second data-path structure according to the presentinvention. In the data path according to the present invention, since anoffset-compensated sub amplifier is disposed in a connection portion ofa local IO line and a main IO line, the offset of the direct senseamplifier can be compensated without providing an offset compensationfor the direct sense amplifier itself. A memory array ARY and a senseamplifier SA therein are identical to those shown in FIG. 1, andtherefore only respective portions thereof are illustrated. What isdifferent in the present invention is that a sub amplifier BA isprovided in the cross area XP. The other circuits except the cross areaare the same to those of FIG. 5 and therefore are omitted in FIG. 21.

An operation of the data path according to the present invention will bedescribed by using operation waveforms of FIG. 22. When the read commandRD is inputted, the pre-charge signal PC is deactivated at the VSS.Almost at the same time, the read enable signal RE is activated at theVCL and the REB is activated at the VSS, whereby the sub amplifier BA isstarted. Furthermore, since the DSAS is driven from the VPC to the VSS,the direct sense amplifier DSA is activated. At this time, the bit line,which is an input of the DSA, remains pre-charged at the VDL/2.Therefore, when the read column select line RYS is activated, a signalcorresponding to an offset of the direct sense amplifier occurs on theread local IO lines RLIO/RLIOB. At this moment, a compensation signal CPis at the VCL, and input terminals GT and GB of the sub amplifierconnected to the LIO and a decoupling capacitance are short-circuitedfrom output terminals thereof to be fixed at an offset compensationpotential. The offset of the sub amplifier itself is compensated at thismoment.

Next, after the CP is deactivated at the VSS to set the sub amplifier inan amplifiable state, the word line WL is activated, thereby causing asignal from the memory cell to occur between the bit lines BL/BLB. Thedirect sense amplifier amplifies it and outputs the signal to the RLIOand RLIOB. At this time, since signals occurs on the GT and GB via adecoupling capacitance, a voltage in which variations of the RLIO andRLIOB are added to the offset compensation potential occurs. Therefore,a signal, in which a reference is set as a potential difference betweenthe RLIO and RLIOB at an instant at which the CP is dropped to the VSS,occurs, so that a net RLIO signal without the offset of the direct senseamplifier is obtained. Accordingly, it is possible to compensate for theoffset of the direct sense amplifier. The sub amplifier amplifies thepotential difference between the GT and GB for the output to the MIO andMIOB.

Thus, to make the offset compensation, the decoupling capacitance and apass transistor are required. However, if they are provided to theindividual direct sense amplifiers, the area of each sense amplifier isextremely increased. By using the data-path structure according to thepresent invention, the operation margin during the reading can beenhanced while the chip size is kept small.

The present invention described above can be used in a high-speed randomaccess memory such as a DRAM or SRAM, particularly, in a memory that thesignal read from the memory cell to the bit line is transmitted to aperipheral circuit at a high speed by a gate-input amplifier. However,the present invention can be used in a non-volatile memory such as aFLASH, FERAM, or MRAM to increase the speed of reading. Furthermore, inthe on-chip memory incorporated in a microprocessor or a logic chip suchas the DSP, since speeding up of the access time is required withimprovement of the clock frequency, there are strong demands forimproving the speed-up more than a stand-alone memory. Therefore, it iseffective that the present invention is applied thereto.

As described above, the invention made by the present inventors has beenspecifically described. However, needless to say, the present inventionis not limited to the above-mentioned embodiments and can be variouslyaltered and modified without departing from the gist thereof.

Main effects obtained from the present invention will be as follows.

Firstly, in the random access memory, since the direct sense amplifieris selectively activated, the power consumption can be significantlyreduced during the read operation. Then, since the load capacitance ofthe local IO line can be reduced, the reading speed can be made faster.Furthermore, data pattern dependency of the load capacitance of thelocal IO line during the read operation is reduced, so that apost-manufacturing test is facilitated.

Secondly, the noise in the direct sense amplifier during a high-speedoperation can be reduced, and thereby the operation margin can beenhanced. Thirdly, the number of bits to be read from a single memoryarray can be doubled without increasing the chip size.

INDUSTRIAL APPLICABILITY

The present invention can be used in a high-speed random access memorysuch as a DRAM or SRAM, particularly, in a memory that the signal readfrom the memory cell to the bit line is transmitted to a peripheralcircuit at a high speed by a gate-input amplifier. Also, the presentinvention can be used in a non-volatile memory such as a FLASH, FERAM,or MRAM to increase the speed of reading. Furthermore, it can be appliedto not only a memory stand-alone chip but also the on-chip memoryincorporated in a microprocessor or a logic chip such as the DSP.

1. A semiconductor memory device comprising: first and second regionseach including a word line extending in a first direction, first andsecond bit lines extending in a second direction intersecting with saidfirst direction, a memory cell connected to said word line and saidfirst and second bit lines, an amplifier circuit for amplifyinginformation read from said memory cell, first and second IO lines forreceiving the read information from said amplifier circuit, and a sourceline for controlling said amplifier circuit; and a column select lineconnected to said first and second regions in common and extending insaid second direction, wherein said amplifier circuit includes first tofourth MOS transistors, a gate of said first MOS transistor is connectedto said first bit line, a gate of said second MOS transistor isconnected to said second bit line, and sources of said first and secondMOS transistors are connected to said source line, a drain of said thirdMOS transistor is connected to said first IO line and a drain of saidfourth MOS transistor is connected to said second IO line, gates of saidthird and fourth MOS transistors included in the amplifier circuitsprovided in said first and second regions are connected to said columnselect line in common, a drain of said first MOS transistor is connectedto a source of said third MOS transistor, a drain of said second MOStransistor is connected to a source of said fourth MOS transistor, in afirst state, potentials of said first and second IO lines included insaid first region are higher than a potential of the source lineincluded in said first region, and the first and second IO linesincluded in said second region and the source line are equal inpotential, and in said first state, information is read from the memorycell included in said first region.
 2. The semiconductor memory deviceaccording to claim 1, wherein said first region includes a plurality ofsaid amplifier circuits and a source-line driver for driving said sourceline, the plurality of said amplifier circuits included in said firstregion are connected to said source line in common, and said source-linedriver is disposed in a region surrounded by a sense amplifier columnprovided with the plurality of said amplifier circuits and a word-drivercolumn provided with a plurality of word drivers for driving said wordline.
 3. The semiconductor memory device according to claim 1, whereinsaid first region includes a plurality of said amplifier circuits and asource-line driver for driving said source line, the plurality of saidamplifier circuits included in said first region are connected to saidsource line in common, said source-line driver is disposed in a regionsurrounded by a sense amplifier column provided with the plurality ofsaid amplifier circuits and a word-driver column provided with aplurality of word drivers for driving said word line, the plurality ofsaid amplifier circuits are connected to said first and second IO linesin common, and a second amplifier circuit for compensating for offsetsof the plurality of said amplifier circuits is connected to said firstand second IO lines.
 4. The semiconductor memory device according toclaim 1, wherein said amplifier circuit further includes a fifth MOStransistor, and a source of said fifth MOS transistor is connected tothe drain of said second MOS transistor, a drain of said fifth MOStransistor is connected to the drain of the first MOS transistor, and agate of said fifth MOS transistor is controlled by a pre-charge signal.5. The semiconductor memory device according to claim 1, wherein saidfirst region further includes a write circuit for writing information tosaid memory cell, a write column select line for selecting said writecircuit, a write control signal line for controlling said write circuit,and a write IO line pair connected to said write circuit, said writecircuit further includes sixth to ninth MOS transistors, gates of saidsixth and seventh MOS transistors are connected to said write columnselect line, a drain of said sixth MOS transistor is connected to one ofsaid write IO line pair, and a drain of said seventh MOS transistor isconnected to the other of said write IO line pair, gates of said eighthand ninth MOS transistors are connected to said write control signalline, a source of said eighth MOS transistor is connected to said firstbit line, and a source of said ninth MOS transistor is connected to saidsecond bit line, and a source of said sixth MOS transistor is connectedto a drain of said eighth MOS transistor, and a source of said seventhMOS transistor is connected to a drain of the ninth MOS transistor. 6.The semiconductor memory device according to claim 1, wherein said firstregion further includes a write circuit for writing information to saidmemory cell, a write column select line for selecting said writecircuit, a write control signal line for controlling said write circuit,and a write IO line pair connected to said write circuit, said writecircuit further includes sixth to ninth MOS transistors, gates of saidsixth and seventh MOS transistors are connected to said write columnselect line, a drain of said sixth MOS transistor is connected to one ofsaid write IO line pair, and a drain of said seventh MOS transistor isconnected to the other of said write IO line pair, gates of said eighthand ninth MOS transistors are connected to said write control signalline, a source of said eighth MOS transistor is connected to said firstbit line, and a source of said ninth MOS transistor is connected to saidsecond bit line, a source of said sixth MOS transistor is connected to adrain of said eighth MOS transistor, and a source of said seventh MOStransistor is connected to a drain of the ninth MOS transistor, and saidwrite column select line is connected to said column select line.
 7. Thesemiconductor memory device according to claim 1, wherein said firstregion further includes a write circuit for writing information to saidmemory cell, a write column select line for selecting said writecircuit, a write control signal line for controlling said write circuit,and a write IO line pair connected to said write circuit, said writecircuit further includes sixth to ninth MOS transistors, gates of saidsixth and seventh MOS transistors are connected to said write columnselect line, a drain of said sixth MOS transistor is connected to one ofsaid write IO line pair, and a drain of said seventh MOS transistor isconnected to the other of said write IO line pair, gates of said eighthand ninth MOS transistors are connected to said write control signalline, a source of said eighth MOS transistor is connected to said firstbit line, and a source of said ninth MOS transistor is connected to saidsecond bit line, a source of said sixth MOS transistor is connected to adrain of said eighth MOS transistor, and a source of said seventh MOStransistor is connected to a drain of the ninth MOS transistor, saidwrite column select line is connected to said column select line, saidwrite circuit further includes a tenth MOS transistor, and a source ofsaid tenth MOS transistor is connected to the source of said sixth MOStransistor, a drain of said tenth MOS transistor is connected to thesource of said seventh MOS transistor, and a gate of said tenth MOStransistor is controlled by a pre-charge signal.
 8. A semiconductormemory device comprising: first and second regions each including a wordline extending in a first direction, first and second bit linesextending in a second direction intersecting with said first direction,a memory cell connected to said word line and said first and second bitlines, an amplifier circuit for amplifying information read from saidmemory cell, first and second IO lines for receiving the readinformation from said amplifier circuit, and a source line forcontrolling said amplifier circuit; and a column select line connectedto said first and second regions in common and extending in said seconddirection, wherein said amplifier circuit includes first to fourth MOStransistors, a gate of said first MOS transistor is connected to saidfirst bit line, a gate of said second MOS transistor is connected tosaid second bit line, and sources of said first and second MOStransistors are connected to said source line, a drain of said third MOStransistor is connected to said first IO line and a drain of said fourthMOS transistor is connected to said second IO line, gates of said thirdand fourth MOS transistors included in the amplifier circuits providedin said first and second regions are connected to said column selectline in common, a drain of said first MOS transistor is connected to asource of said third MOS transistor, a drain of said second MOStransistor is connected to a source of said fourth MOS transistor, in afirst state, potentials of said first and second IO lines included insaid first region are higher than a potential of the source lineincluded in said first region, potentials of said first and second IOlines and a potential of the source included in said second region arehigher than absolute value of a value obtained by subtracting athreshold voltage of said first and second MOS transistors from apotential of said first and second bit lines, and in said first state,information is read from the memory cell included in said first region.9. The semiconductor memory device according to claim 8, wherein saidfirst region includes a plurality of said amplifier circuits and asource-line driver for driving said source line, the plurality of saidamplifier circuits included in said first region are connected to saidsource line in common, and said source-line driver is disposed in aregion surrounded by a sense amplifier column provided with theplurality of said amplifier circuits and a word-driver column providedwith a plurality of word drivers for driving said word line.
 10. Thesemiconductor memory device according to claim 8, wherein said firstregion includes a plurality of said amplifier circuits and a source-linedriver for driving said source line, the plurality of said amplifiercircuits included in said first region are connected to said source linein common, said source-line driver is disposed in a region surrounded bya sense amplifier column provided with the plurality of said amplifiercircuits and a word-driver column provided with a plurality of worddrivers for driving said word line, the plurality of said amplifiercircuits are connected to said first and second IO lines in common, anda second amplifier circuit for compensating for offsets of the pluralityof said amplifier circuits is connected to said first and second IOlines.
 11. The semiconductor memory device according to claim 8, whereinsaid amplifier circuit further includes a fifth MOS transistor, and asource of said fifth MOS transistor is connected to the drain of saidsecond MOS transistor, a drain of said fifth MOS transistor is connectedto the drain of the first MOS transistor, and a gate of said fifth MOStransistor is controlled by a pre-charge signal.
 12. The semiconductormemory device according to claim 8, wherein said first region furtherincludes a write circuit for writing information to said memory cell, awrite column select line for selecting said write circuit, a writecontrol signal line for controlling said write circuit, and a write IOline pair connected to said write circuit, said write circuit furtherincludes sixth to ninth MOS transistors, gates of said sixth and seventhMOS transistors are connected to said write column select line, a drainof said sixth MOS transistor is connected to one of said write IO linepair, and a drain of said seventh MOS transistor is connected to theother of said write IO line pair, gates of said eighth and ninth MOStransistors are connected to said write control signal line, a source ofsaid eighth MOS transistor is connected to said first bit line, and asource of said ninth MOS transistor is connected to said second bitline, and a source of said sixth MOS transistor is connected to a drainof said eighth MOS transistor, and a source of said seventh MOStransistor is connected to a drain of the ninth MOS transistor.
 13. Thesemiconductor memory device according to claim 8, wherein said firstregion further includes a write circuit for writing information to saidmemory cell, a write column select line for selecting said writecircuit, a write control signal line for controlling said write circuit,and a write IO line pair connected to said write circuit, said writecircuit further includes sixth to ninth MOS transistors, gates of saidsixth and seventh MOS transistors are connected to said write columnselect line, a drain of said sixth MOS transistor is connected to one ofsaid write IO line pair, and a drain of said seventh MOS transistor isconnected to the other of said write IO line pair, gates of said eighthand ninth MOS transistors are connected to said write control signalline, a source of said eighth MOS transistor is connected to said firstbit line, and a source of said ninth MOS transistor is connected to saidsecond bit line, a source of said sixth MOS transistor is connected to adrain of said eighth MOS transistor, and a source of said seventh MOStransistor is connected to a drain of the ninth MOS transistor, and saidwrite column select line is connected to said column select line. 14.The semiconductor memory device according to claim 8, wherein said firstregion further includes a write circuit for writing information to saidmemory cell, a write column select line for selecting said writecircuit, a write control signal line for controlling said write circuit,and a write IO line pair connected to said write circuit, said writecircuit further includes sixth to ninth MOS transistors, gates of saidsixth and seventh MOS transistors are connected to said write columnselect line, a drain of said sixth MOS transistor is connected to one ofsaid write IO line pair, and a drain of said seventh MOS transistor isconnected to the other of said write IO line pair, gates of said eighthand ninth MOS transistors are connected to said write control signalline, a source of said eighth MOS transistor is connected to said firstbit line, and a source of said ninth MOS transistor is connected to saidsecond bit line, a source of said sixth MOS transistor is connected to adrain of said eighth MOS transistor, and a source of said seventh MOStransistor is connected to a drain of the ninth MOS transistor, saidwrite column select line is connected to said column select line, saidwrite circuit further includes a tenth MOS transistor, and a source ofsaid tenth MOS transistor is connected to the source of said sixth MOStransistor, a drain of said tenth MOS transistor is connected to thesource of said seventh MOS transistor, and a gate of said tenth MOStransistor is controlled by a pre-charge signal.
 15. A semiconductormemory device comprising: first and second regions each including a wordline extending in a first direction, a plurality of bit line pairsextending in a second direction intersecting with said first direction,a plurality of memory cells connected to said word line and saidplurality of bit line pairs, an amplifier circuit for amplifyinginformation read from said memory cells, first and second IO lines forreceiving the read information from said amplifier circuit, a sourceline for controlling said amplifier circuit, and selecting means forselecting a signal inputted to said amplifier circuit; and a columnselect line connected to first and second regions in common andextending in said second direction, wherein said amplifier circuitincludes first to fourth MOS transistors, gates of said first and secondMOS transistors receives an input of said selecting means, and sourcesof said first and second MOS transistors are connected to said sourceline, a drain of said third MOS transistor is connected to said first IOline, and a drain of said fourth MOS transistor is connected to saidsecond IO line, each gate of said third and fourth MOS transistorsincluded in said amplifier circuit is connected to said column selectline in common, a drain of said first MOS transistor is connected to asource of said third MOS transistor, a drain of said second MOStransistor is connected to a source of said fourth MOS transistor, andsignals of said plurality of bit line pairs are inputted to saidselecting means.
 16. The semiconductor memory device according to claim15, wherein said semiconductor memory device is such that, in a firststate, potentials of said first and second IO lines included in saidfirst region are higher than a potential of said source line included insaid first region, and potentials of said first and second IO linesincluded in said second region and of said source line are equal to ormore than an absolute value of a value obtained by subtracting athreshold voltage of said first and second MOS transistors from apotential of said plurality of bit line pairs included in said secondregion.
 17. The semiconductor memory device according to claim 16,wherein said memory cell includes two transistors and two capacitors,and said selecting means is a multiplexer.
 18. The semiconductor memorydevice according to claim 15, wherein said memory cell includes twotransistors and two capacitors, and said selecting means is amultiplexer.
 19. A semiconductor memory device comprising: first andsecond regions each including a word line extending in a firstdirection, a plurality of bit lines extending in a second directionintersecting with said first direction and having first and second bitlines, a plurality of memory cells connected to said word line and saidplurality of bit lines, first and second circuit columns each providedwith an amplifier circuit for amplifying information read from saidmemory cells and a write circuit for writing the information to saidmemory cells, first and second IO line pairs connected to said circuitcolumns and extending in said first direction, and a source lineconnected to said amplifier circuits; and first and second read columnselect lines and first and second write column select lines connected tosaid first and second regions in common, wherein said first and secondread column select lines and said first and second write column selectlines extend in said second direction, each of the amplifier circuitsprovided in the first and second circuit columns has first to fourth MOStransistors, a gate of said first MOS transistor is connected to saidfirst bit line, a gate of said second MOS transistor is connected tosaid second bit line, and sources of said first and second MOStransistors are connected to said source line, a drain of said first MOStransistor is connected to a source of said third MOS transistor, adrain of said second MOS transistor is connected to a source of saidfourth MOS transistor, a drain of the third MOS transistor of theamplifier circuit included in said first circuit column is connected toone of the first IO line pair connected to said write column select lineincluded in said second circuit column, and a drain of said fourth MOStransistor is connected to the other of the first IO line pair connectedto the write circuit included in said second circuit column, a drain ofthe third MOS transistor of the amplifier circuit included in saidsecond circuit column is connected to one of the second IO line pairconnected to the write circuit included in said first circuit column,and the drain of the fourth MOS transistor is connected to the other ofthe second IO line pair connected to the write circuit included in saidfirst circuit column, the write circuit included in said first circuitcolumn is connected to said first write column select line, the writecircuit included in said second circuit column is connected to saidsecond write column select line, gates of the third and fourth MOStransistors in the amplifier circuit of said first circuit columnincluded in said first region and gates of the third and fourth MOStransistors in the amplifier circuit of said first circuit columnincluded in said second region are connected to said first read columnselect line in common, gates of the third and fourth MOS transistors inthe amplifier circuit of said second circuit column included in saidfirst region and gates of the third and fourth MOS transistors in theamplifier circuit of said second circuit column included in said secondregion are connected to said second read column select line in common,in a first state, said first and second read column select lines areactivated, and potentials of said first and second IO line pairsincluded in said first region are higher than a potential of the sourceline included in said first region, and the first and second IO linepairs included in said second region and the source line are equal inpotential, or potentials of the first and second IO lines and apotential of said source line included in said second region are higherthan an absolute value of a value obtained by subtracting a thresholdvoltage of said first and second MOS transistors from a potential ofsaid first and second bit lines.